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Techreport has learned that a chip-level problem has impacted the supply of these chips to both server OEMs and distribution channel customers. It is related to the translation lookaside buffer (TLB) in the processor’s L3 cache. The erratum can cause a system hang with certain software workloads. The erratum is present in all AMD quad-core...

The post L3 Erratum Impacts Opteron & Phenom Performance appeared first on VR-Zone.

L3 Erratum Impacts Opteron & Phenom Performance

Techreport has learned that a chip-level problem has impacted the supply of these chips to both server OEMs and distribution channel customers. It is related to the translation lookaside buffer (TLB) in the processor’s L3 cache. The erratum can cause a system hang with certain software workloads. The erratum is present in all AMD quad-core...

The post L3 Erratum Impacts Opteron & Phenom Performance appeared first on VR-Zone.